Semiconductor devices such as transistors or diodes formed by using a silicon carbide substrate (SiC substrate) where Si and C are bonded at a component ratio of 1:1 are expected to be put to practical use as power devices. Since silicon carbide is a wide band gap semiconductor and a breakdown electric field thereof is an order of magnitude higher than that of silicon, a high reverse breakdown voltage can be maintained even if the thickness of a depletion layer in a pn junction or a Schottky junction is reduced. Thus, the use of the silicon carbide substrate allows the thickness of the device to be reduced and a doping concentration to be increased. Therefore, it is expected that a low-loss power device having low on-resistance and high breakdown voltage will be realized.
There is a disadvantage that a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed by using a silicon carbide substrate has lower mobility of carriers in a channel region (channel mobility) than that of a MOSFET formed by using a silicon substrate. This is mainly because a large amount of carbon remains in a thermal oxide film on the silicon carbide substrate intrinsically and a high interface state is created in a region near a boundary surface with the thermal oxide film of a silicon carbide layer. Furthermore, a substrate having a 4H or 6H polytype is used as the silicon carbide substrate, and in order to achieve smooth epitaxial growth, a substrate having a main surface offset at approximately 8° with respect to a {0001} surface is used. At a surface of the silicon carbide substrate having been annealed at a high temperature after dopant implantation, however, random irregularities exist. These irregularities cause the interface state density to be increased when the thermal oxide film as a gate insulating film is formed, and the thermal oxide film is also susceptible to carrier scattering caused by the irregularities at the surface.
As an art for alleviating the impact of the irregularities at the surface in the above-described silicon carbide substrate, Japanese Patent Laying-Open No. 2000-294777 (Patent Document 1) discloses an art for forming a channel region in a special terrace portion. After ion implantation to the silicon carbide substrate in order to form a diffusion region, annealing is performed at a high temperature, for example, to activate the dopant. Then, bunching steps are formed as a result of formation and buildup of steps and a flat terrace surface is formed between the bunching steps. In Patent Document 1, a region immediately under this flat terrace surface of the bunching steps is used as the channel region, so that the interface state caused by the irregularities at the surface is reduced and the carrier scattering caused by the irregularities at the surface is lessened.
Patent Document 1: Japanese Patent Laying-Open No. 2000-294777